SH7619_09 Datasheet, PDF (718/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
22.14 Guidelines for Layout
22.14.1 General Guidelines
The guidelines for four-layer boards are shown below.
(1) Configuration of Board Layers
• Layer 1: Top layer (component side), which is a signal layer
• Layer 2: Ground layer
• Layer 3: Power layer
• Layer 4: Bottom layer (solder side), which is a signal layer
(2) Impedance Control
Ideally, impedance control should satisfy the following.
• Single ended traces: 51 ohm ±10%
• Differential pairs: 99 ohm ±10%
• No restrictions on the impedance of short power/grand traces
(3) Vias
Vias are a source of impedance mismatches and distorted waveforms on transmission lines, which
can cause problems of signal integrity (noise) and EMI issues. For differential signals and fast
signal traces, avoid using vias on the signal lines whenever possible. If vias are used on such
signal traces, ensure that they do not create problems by simulation or other means.
(4) Notes on Routing
Stubs (branching) cause signal reflections, so they should be 12.7 mm (0.5 inch) or shorter for
critical nets.
Stagger is a bad source of crosstalk, so all the signal traces around the PHY should be 25.4 mm (1
inch) or shorter.
Rev. 6.00 Jul. 15, 2009 Page 678 of 816
REJ09B0237-0600