SH7619_09 Datasheet, PDF (315/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
Bit
Bit Name value R/W Description
21
TC
0
R/W Frame Transmit Complete
Indicates that all the data specified by the transmit
descriptor has been transmitted to the EtherC. The
transfer status is written back to the relevant
descriptor. For 1-frame/1-buffer processing, when 1-
frame transmission is completed and the transmission
descriptor valid bit (TACT) in the next descriptor is not
set, transmission is completed and this bit is set to 1.
Likewise, for multiple-frame buffer processing, when
the last data in the frame is transmitted and the
transmission descriptor valid bit (TACT) in the next
descriptor is not set, transmission is completed and
this bit is set to 1. After frame transmission, the E-
DMAC writes the transmission status back to the
descriptor.
0: Transfer not complete, or no transfer directive
1: Transfer complete
20
TDE
0
R/W Transmit Descriptor Empty
Indicates that the transmission descriptor valid bit
(TACT) in the descriptor is not set when the E-DMAC
reads the transmission descriptor when the previous
descriptor is not the last one of the frame for multiple-
buffer frame processing. As a result, an incomplete
frame may be transmitted.
0: Transmit descriptor active bit TACT = 1 detected
1: Transmit descriptor active bit TACT = 0 detected
When transmission descriptor empty (TDE = 1)
occurs, execute a software reset and initiate
transmission. In this case, the address that is stored in
the transmit descriptor list address register (TDLAR) is
transmitted first.
19
TFUF
0
R/W Transmit FIFO Underflow
Indicates that underflow has occurred in the transmit
FIFO during frame transmission. Incomplete data is
sent onto the line.
0: Underflow has not occurred
1: Underflow has occurred
Rev. 6.00 Jul. 15, 2009 Page 275 of 816
REJ09B0237-0600