SH7619_09 Datasheet, PDF (96/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
3.2 Register Descriptions
The cache has the following registers. For details on register addresses and register states during
each process, refer to section 24, List of Registers.
• Cache control register 1 (CCR1)
3.2.1 Cache Control Register 1 (CCR1)
The cache is enabled or disabled by the CE bit in CCR1. CCR1 also has the CF bit (which
invalidates all cache entries), and the WT and CB bits (which select either write-through mode or
write-back mode). Programs that change the contents of CCR1 should be placed in the address
space that is not cached.
Bit
31 to 4
3
2
1
Initial
Bit Name Value
—
All 0
CF
0
CB
0
WT
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Cache Flush
Writing 1 flushes all cache entries meaning that it
clears the V, U, and LRU bits of all cache entries to
0. This bit is always read as 0. Write-back to external
memory is not performed when the cache is flushed.
R/W Write-Back
Indicates the cache operating mode for H'80000000
to H'9FFFFFFF.
0: Write-through mode
1: Write-back mode
R/W Write-Through
Indicates the cache operating mode for H'00000000
to H'7FFFFFFF and H'C0000000 to H'DFFFFFFF.
0: Write-back mode
1: Write-through mode
Rev. 6.00 Jul. 15, 2009 Page 56 of 816
REJ09B0237-0600