SH7619_09 Datasheet, PDF (676/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
The data on the CO_MDO and CO_MDI lines is latched on the rising edge of the CO_MDC. The
frame structure and timing of the data is shown in figure 22.4 and figure 22.5.
CO_MDC
Output on the rising edge
Latch on the rising edge
...
CO_MDI ^{32 1's 0 1 1 0} A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
CO_MDIO_DIR
CO_MDO
Preamble
Start of
Frame
OP
Code
PHY Address
Register Address
D15 D14
Turn
Around
...
Data
D1 D0
Figure 22.4 MDIO Timing and Frame Structure (READ Cycle)
CO_MDC
Output on the rising edge
Latch on the rising edge
CO_MDI ^{32 1's 0 1 0 1} A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
D15 D14
CO_MDIO_DIR
CO_MDO
Preamble
Start of
Frame
OP
Code
PHY Address
Register Address
Turn
Around
...
... ^{D1 D0}
Data
Figure 22.5 MDIO Timing and Frame Structure (WRITE Cycle)
Shown below is an example of coding for MDC cycles implemented by software loops.
Note: CO_MDIO_DIR in figures 22.4 and 22.5 above has a reverse polarity in relation to the
MMD bit in the PIR register.
Rev. 6.00 Jul. 15, 2009 Page 636 of 816
REJ09B0237-0600