SH7619_09 Datasheet, PDF (779/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 25 Electrical Characteristics
25.4.2 Control Signal Timing
Table 25.8 Control Signal Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.71 V to 1.89 V; for Ta, see the operating
temperatures given in appendix B, Product Code Lineup.
Item
Symbol Min.
Max.
Reference
Unit Figures
RES pulse width
RES setup time*¹
t
RESW
t
RESS
20*²

25

t *3
bcyc
Figures 25.7 and
ns ^25.8
RES hold time
t_RESH
15

ns
NMI setup time*¹
t_NMIS
12

ns Figure 25.8
NMI hold time
t_NMIH
10

ns
IRQ7 to IRQ0 setup time*¹
t
12

ns
IRQS
IRQ7 to IRQ0 hold time
t
10

ns
IRQH
Bus tri-state delay time 1
t

20
ns Figure 25.9
BOFF1
Bus tri-state delay time 2
t

20
ns
BOFF2
Bus buffer on time 1
t_BON1

20
ns
Bus buffer on time 2
t

20
ns
BON2
Notes: 1. The RES, NMI, and IRQ7 to IRQ0 signals are asynchronous signals. When the setup
time is satisfied, a signal change is detected at the rising edge of the clock signal. When
the setup time is not satisfied, a signal change may be delayed to the next rising edge.
2. In standby mode, t = t (10 ms). When changing the clock multiplication, t = t
RESW
OSC2
RESW
PLL1
(100 µs).
3. t_bcyc indicates the period of the external bus clock (Bφ).
CKIO
RES
t_RESS
t_RESW
t_RESS
Figure 25.7 Reset Input Timing
Rev. 6.00 Jul. 15, 2009 Page 739 of 816
REJ09B0237-0600