SH7619_09 Datasheet, PDF (482/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
M = (0.5 - ¹ ) = (L - 0.5) F - ^{D - 0.5} (1+F) × 100 %
2N
N
Where: M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
When D = 0.5 and F = 0:
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
6. Prohibited Multiple Pin Allocation for Channel 1
Although signals SCK1, RxD1, and TxD1 can be respectively assigned to multiple pins of
PD4 or PE20, PD3 or PE19, and PD2 or PE18, either of them must be selected. For example, if
signal SCK1 is assigned to both pins PD4 and PE20, correct operation of the SCIF is not
guaranteed.
7. Status of the TxD and RTS Pins When the TE Bit is Cleared
The TxDi (i = 0, 1, 2) and RTSj (j = 0, 1) pins usually function as output pins during serial
communication. However, even if these functions are selected by the pin function controller
(PFC), the internal weak keeper drives the pins to unstable levels as long as the TE bit in
SCSCRi (i = 0, 1, 2) is cleared. To make these pins always function as output pins (regardless
of the value of the TE bit), set SCSPTRi (i = 0, 1, 2) and PFC in the following order.
a. Set the SPBIO and SPBDT bits in SCSPTRi (i = 0, 1, 2). Set the RTSIO and RTSDT bits in
SCSPTRj (j = 0, 1).
b. Select the TxDi (i = 0, 1, 2) and RTSj (j = 0, 1) pins with the PFC.
8. Interval from when the TE bit in SCSCR is Set to 1 until a Start Bit is Transmitted in
Asynchronous Mode
In the SCIF included in former products, a start bit is transmitted after the internal equivalent
to one frame. In the SCIF included in this product, however, a start bit is transmitted directly
after the TE bit is set to 1.
Rev. 6.00 Jul. 15, 2009 Page 442 of 816
REJ09B0237-0600