SH7619_09 Datasheet, PDF (571/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
17.7 Interface (Details)
17.7.1 HIFIDX Write/HIFGSR Read
Writing of HIFIDX and reading of HIFGSR are shown in figure 17.4.
HIFCS
HIFRS
HIFRD
HIFWR
HIFD15 to HIFD00
HIFIDX write cycle HIFGSR read cycle
WT_D
RD_D
Figure 17.4 HIFIDX Write and HIFGSR Read
17.7.2 Reading/Writing of HIF Registers other than HIFIDX and HIFGSR
As shown in figure 17.5, in reading and writing of HIF internal registers other than HIFIDX and
HIFGSR, first HIFRS is held high and HIFIDX is written to in order to select the register to be
accessed and the byte location. Then HIFRS is held low, and reading or writing of the register
selected by HIFIDX is performed.
HIFCS
HIFRS
HIFRD
HIFWR
HIFD15 to HIFD00
Index write
Register write
Register read
HIFIDX
Register selection
WT_D
RD_D
Figure 17.5 HIF Register Settings
Rev. 6.00 Jul. 15, 2009 Page 531 of 816
REJ09B0237-0600