SH7619_09 Datasheet, PDF (712/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(b) Adjustment Register for Tx10 Waveform Output
Note: This register has little effect. The following descriptions of the register are only for your
reference.
The adjustment register for Tx10 waveform output has DnTAMP (n = 1, 0) bits to adjust the
amplitude of waveforms and DnTCMP (n = 1, 0) bits to adjust the slope of waveforms. The
number of the register is 23 (decimal). When the value of writing of the step 8 in the adjustment
register for Tx100 waveform output, described in (a), is H’4418 instead of H’4416, the value of
writing of the step 7 is written as the setting value for the adjustment register for Tx10 waveform
output. As described in the table below, the values written in bit15 and bit14 in the adjustment
register for Tx10 waveform output are used as the setting values for DnTAMP (n = 1, 0) bits,
while the values written in bit13 and bit12 are used as the setting values for DnTCMP (n = 1, 0)
bits. However, based our testing, the adjustment of the amplitude by DnTAMP (n = 1, 0) bits
effects only in several millivolts.
• Adjustment register for Tx10 waveform output
Initial
Bit
Bit Name Value R/W
Description
15
D1TAMP 0
R/W
These bits adjust the amplitude.
14
D0TAMP 1
R/W
11: Amp 2 stp+
10: Amp 1 stp+
01: Regular
00: Amp 1 stp-
13
D1TCMP 0
12
D0TCMP 0
R/W
These bits adjust the slope (transition time) (the more
R/W
steps up, the gentler the slope is).
11: Three steps up
10: Two steps up
01: One step up
00: Regular
11 to 0 
0
RO
Reserved
The write value should always be 0.
Rev. 6.00 Jul. 15, 2009 Page 672 of 816
REJ09B0237-0600