SH7619_09 Datasheet, PDF (720/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(2) Sample Placement
1. The pulse transformer should be placed close to the PHY-related pins of this LSI.
2. Components should be placed so that the signal traces of differential pairs, TxP/TxM and
RxP/RxM, do not cross each other.
3. R4 and R5, which are terminating resistors, should be placed close to this LSI.
4. R1 and R2 should be placed close to the pulse transformer (RJ45).
5. R3 and C4, which form a filter, should be placed close to the pulse transformer (RJ45).
6. C4 of the center tap should be placed close to the pulse transformer (RJ45).
7. Do not place any components on the bottom side.
(3) Ground Planes
Layer 2 is divided into logic ground plane and frame ground plane.
The logic ground is the combination of digital ground and analog ground. The frame ground is
connected to the system ground and the shielding of the RJ45 socket so that it is grounded.
Beware that this ground plane cuts impact the routing on adjacent signal layers.
Signal traces of L1 and L4 should not run across the cuts in the ground plane to avoid impedance
mismatches and EMI problems. Minimize the frame ground area so as to make the logic ground as
large and solid as possible. Connect the logic ground and frame ground by a ferrite bead or thick
signal trace to provide a DC path. For safety, exclude the area near the leads of the RJ45 from the
ground area.
(4) Common Power Plane
Layer 3 consists of multiple power planes of Vcc and Vcc for PLL1 and PLL2, which supply 1.8
V, and VccQ and VccnA (n = 1 to 3), which supply 3.3 V. VccnA is made up of an area of analog
power for the RJ45 (connector-type pulse transformer) and an area of analog power for this LSI.
(5) Sample Routing
In the above example, the ground layer is simply divided into two planes while the power layer is
divided into more planes. Therefore, the top layer (component side) is superior to the bottom layer
(solder side) in terms of signal integrity. If possible, all the critical signals of the PHY, differential
signal pairs for example, should be wired in the top layer without any vias.
Another important thing to be noted about differential signal pairs is that the pair of traces of a
pair must be strictly equal in length to minimize duty cycle distortion and common mode
radiation.
Rev. 6.00 Jul. 15, 2009 Page 680 of 816
REJ09B0237-0600