SH7619_09 Datasheet, PDF (98/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
Address
31
12 11 4 3 2 10
Entry selection
Longword (LW) selection
Ways 0 to 3
Ways 0 to 3
0 V U Tag address
1
LW0 LW1 LW2 LW3
255
CMP0 CMP1 CMP2 CMP3
Hit signal 1
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
Figure 3.2 Cache Search Scheme
3.3.2 Read Access
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU bits are updated so that they point to the most recently hit way.
Read Miss: An external bus cycle starts and the entry is updated. The way to be replaced is shown
in table 3.1. Data is updated in units of 16 bytes by updating the entry. When the desired
instruction or data is loaded from external memory to the cache, the instruction or data is
transferred to the CPU in parallel. When it is loaded to the cache, the U bit is cleared to 0, the V
bit is set to 1, the LRU bits are updated so that they point to the most recently hit way. When the U
bit of the entry which is to be replaced by entry updating in write-back mode is 1, the cache-
update cycle starts after the entry is transferred to the write-back buffer. After the cache completes
its update cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte
units.
Rev. 6.00 Jul. 15, 2009 Page 58 of 816
REJ09B0237-0600