SH7619_09 Datasheet, PDF (739/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 24 List of Registers
Register Name
Number
Abbreviation of Bits Address
Module Access Size
Automatic PAUSE frame set register APR
32
H'FB0001B8 EtherC 32
Manual PAUSE frame set register MPR
32
H'FB0001BC EtherC 32
Automatic PAUSE frame retransfer TPAUSER 32
count set register
H'FB0001C4 EtherC 32
Break data register B
BDRB
32
H'FFFFFF90 UBC
32
Break data mask register B
BDMRB
32
H'FFFFFF94 UBC
32
Break control register
BRCR
32
H'FFFFFF98 UBC
32
Execution times break register
BETR
16
H'FFFFFF9C UBC
16
Break address register B
BARB
32
H'FFFFFFA0 UBC
32
Break address mask register B
BAMRB
32
H'FFFFFFA4 UBC
32
Break bus cycle register B
BBRB
16
H'FFFFFFA8 UBC
16
Branch source register
BRSR
32
H'FFFFFFAC UBC
32
Break address register A
BARA
32
H'FFFFFFB0 UBC
32
Break address mask register A
BAMRA
32
H'FFFFFFB4 UBC
32
Break bus cycle register A
BBRA
16
H'FFFFFFB8 UBC
16
Branch destination register
BRDR
32
H'FFFFFFBC UBC
32
Cache control register 1
CCR1
32
H'FFFFFFEC Cache 32
Note: * The numbers of access cycles are eight bits when reading and 16 bits when writing.
Rev. 6.00 Jul. 15, 2009 Page 699 of 816
REJ09B0237-0600