SH7619_09 Datasheet, PDF (162/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 3, 4, 5B, 6B)
CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register
varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or TYPE0)
specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the
target area. Specify CSnBCR first, then specify CSnWCR.
Normal Space, Byte-Selection SRAM:
• CS0WCR
Initial
Bit
Bit Name Value R/W
31 to 13 
All 0 R
12
SW1
0
R/W
11
SW0
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 6.00 Jul. 15, 2009 Page 122 of 816
REJ09B0237-0600