SH7619_09 Datasheet, PDF (154/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Physical Address
Area
Memory to be Connected
Capacity
H'18000000 to H'1BFFFFFF Area 6*² Normal memory
64 Mbytes
Byte-selection SRAM
PCMCIA
H'1C000000 to H'1FFFFFFF Area 7
Reserved area*¹
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. For area 5, CS5BBCR and CS5BWCR are enabled.
For area 6, CS6BBCR and CS6BWCR are enabled.
7.3.4 Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, the bus width is selected
from 8 bits and 16 bits at a power-on reset by the external pin setting. The bus width of other areas
is set by the register. The correspondence between the memory type, external pin (MD3), and bus
width is listed in table 7.4.
Table 7.4 Correspondence between External Pin (MD3), Memory Type, and Bus Width
for CS0
MD3
1
0
Memory Type
Normal memory
Bus Width
8 bits
16 bits
7.3.5 Data Alignment
This LSI supports the big endian and little endian methods of data alignment. The data alignment
is specified using the external pin (MD5) at a power-on reset as shown in table 7.5.
Table 7.5 Correspondence between External Pin (MD5) and Endians
MD5
0
1
Endian
Big endian
Little endian
Rev. 6.00 Jul. 15, 2009 Page 114 of 816
REJ09B0237-0600