SH7619_09 Datasheet, PDF (703/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(6) Reset
The core PHY has 4 reset sources:
• Module reset (co_resetb):
It is connected to the co_resetb of PHYIFCR, and to the internal POR signal.
If the co_resetb is asserted(write "0"), it should be held "0" for at least 100 us to ensure that the
core is properly reset.
• The Power-On-Reset (POR) :
POR(Power-On-Reset) signal, which is driven out of the core through the co_pwruprst of
PHYIFSR, is asserted for approximately 16 ms after the first time that power is supplied to the
chip.
• Software (SW) reset: (Do not use with this product.)
Activated by writing register 0, bit 15 high. This signal is self- clearing. After the register-
write, internal logic extends the reset by 256µs to allow PLL-stabilization before releasing the
logic from reset.
The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be
completed within 0.5s from the setting of this bit.
• Power-Down reset:
Automatically activated when the PHY comes out of power-down mode. The internal power-
down reset is extended by 256µs after exiting the power-down mode to allow the PLLs to
stabilize before the logic is released from reset.
These 4 reset sources are Module reset(Low active) and none Module reset(PHY power on reset,
software reset, power down reset(High active) combined together in the digital block to create the
internal "general reset", SYSRST, which is an asynchronous reset and is active HIGH. This
SYSRST directly drives the PCS, DSP and MII blocks. It is also input to the Central Bias block in
order to generate a short reset for the PLLs.
The SMI mechanism and registers are reset only by the Module reset, PHY power-on reset and
Software reset. During Power-Down, the SMI registers are not reset. Note that some SMI register
bits are not cleared by Software reset - these are marked "NASR" in the register tables.
For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to
25 MHz if auto-negotiation is enabled.
Rev. 6.00 Jul. 15, 2009 Page 663 of 816
REJ09B0237-0600