SH7619_09 Datasheet, PDF (840/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Item
Page Revision (See Manual for Details)
16.4.7 Transmit and Receive 487
Procedures
Transmission/Reception and
Transmission in Master Mode:
Amended
Figure 16.9 (1) shows an example of settings and
operation for master mode transmission/reception. Figure
16.9 (2) shows an example of settings and operation for
master mode transmission.
Figure 16.9 (1)
488
Transmission/Reception
Operation in Master Mode
(Example of Reception and
Full-Duplex Transmission by
the CPU with TDMAE=0)
Replaced from Figure 16.9, Example of Transmit Operation
in Master Mode
Figure 16.9 (2) Transmission 489
Operation in Master Mode
(Example of Half-Duplex
Transmission by the CPU with
TDMAE=0)
Added
16.4.9 Transmit and Receive 500, Added
Timing
501
[Notes on Usage]
18.2 Notes on Usage
577 Added
19.6 Usage Notes
591 Amended
2. The weak keeper circuit is included in all pins except
MD5, MD3, MD2, MD1, MD0, ASEMD, TESTMD,
EXTAL, XTAL, TxP, TxM, RxP, RxM, EXRES1, and
TSTBUSA. The weak keeper is a circuit, always
operating while the power is on, that fixes the input in
I/O pins to low or high when the pins are not driven
from outside. Notes on processing the input pins are as
follows:
 When using pins having the weak keeper circuit as
input pins and driving these pins to a certain level
from outside, adjust the resistance of pull-up/pull-
down resistors to let the weak keeper circuit keep
the intended levels. (2 kΩ and 8 kΩ are
recommended respectively.) The larger the
resistance is, the longer the transition time is. In
addition, a large resistance may fail to let the weak
keeper circuit to keep the intended levels.
Therefore, when the resistors adjusted
comparatively large are used, ensure that any
transition does not delay in the system.
Rev. 6.00 Jul. 15, 2009 Page 800 of 816
REJ09B0237-0600