SH7619_09 Datasheet, PDF (488/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16.3 Register Descriptions
The SIOF has the following registers. For the addresses of these registers and the register states in
each operating state, refer to section 24, List of Registers. In the register descriptions following
this section, channel numbers are omitted.
Channel 0:
• Mode register_0 (SIMDR_0)
• Control register_0 (SICTR_0)
• Transmit data register_0 (SITDR_0)
• Receive data register_0 (SIRDR_0)
• Transmit control data register_0 (SITCR_0)
• Receive control data register_0 (SIRCR_0)
• Status register_0 (SISTR_0)
• Interrupt enable register_0 (SIIER_0)
• FIFO control register_0 (SIFCTR_0)
• Clock select register_0 (SISCR_0)
• Transmit data assign register_0 (SITDAR_0)
• Receive data assign register_0 (SIRDAR_0)
• Control data assign register_0 (SICDAR_0)
• SPI control register_0 (SPICR_0)
Rev. 6.00 Jul. 15, 2009 Page 448 of 816
REJ09B0237-0600