SH7619_09 Datasheet, PDF (682/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
22.4.2 SMI Register Mapping
The following registers are supported (register numbers are in decimal):
Register #
0
1
2
3
4
5
6
Description
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Group
Basic
Basic
Extended
Extended
Extended
Extended
Extended
• SMI Register Format
The mode key is as follows:
RW = read/write, SC = self clearing, WO = write only, RO = read only
LH = latch high, clear on read of register
LL = latch low, clear on read of register
NASR = Not Affected by Software Reset
(n,m) = register n, bit m
Rev. 6.00 Jul. 15, 2009 Page 642 of 816
REJ09B0237-0600