SH7619_09 Datasheet, PDF (526/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
The number of stages of the FIFO is always sixteen even if the data area or empty area exceeds the
FIFO size (the number of FIFOs). Accordingly, an overflow error or underflow error occurs if data
area or empty area exceeds sixteen FIFO stages. The FIFO transmit or receive request is canceled
when the above condition is not satisfied even if the FIFO is not empty or full.
Number of FIFOs: The number of FIFO stages used in transmission and reception is indicated by
the following register.
• Transmit FIFO: The number of empty FIFO stages is indicated by the TFUA4 to TFUA0 bits
in SIFCTR.
• Receive FIFO: The number of valid data stages is indicated by the RFUA4 to RFUA0 bits in
SIFCTR.
The above indicate possible data numbers that can be transferred by the CPU or DMAC.
Rev. 6.00 Jul. 15, 2009 Page 486 of 816
REJ09B0237-0600