SH7619_09 Datasheet, PDF (190/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
carried out. Therefore, care must be taken when controlling the buffers with the RD/WR signal, to
avoid data conflict.
Figures 7.4 and 7.5 show the basic timings of normal space consecutive access. If the WM bit in
CSnWCR is cleared to 0, a Tnop cycle is inserted to check the external wait (figure 7.4). If the
WM bit in CSnWCR is set to 1, an external wait request is ignored and no Tnop cycle is inserted
(figure 7.5).
CKIO
T1
T2
Tnop
T1
T2
A25 to A0
CSn
RD/WR
RD
Read
D
Write
WEn(BEn)
D
BS
WAIT
Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 bits,
Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0)
Rev. 6.00 Jul. 15, 2009 Page 150 of 816
REJ09B0237-0600