SH7619_09 Datasheet, PDF (704/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(7) LED Description
The PHY provides four LED signals. These provide a convenient means to determine the mode of
operation of the core. All LED signals are active low.
• The CRS LED :
Its output is driven low when CRS is active (high). When CRS becomes inactive, the Activity
LED output is extended by 128 ms.
• The Link LED:
Its output is driven low whenever the PHY detects a valid link. The use of the 10Mbps or
100Mbps link test status is determined by the condition of the internally determined speed
selection.
• The Speed LED:
Its output is driven low when the operating speed is 100Mbit/s or during Auto-negotiation.
This LED will go inactive when the operating speed is 10Mbit/s.
• The Full-Duplex LED
Its output is driven low when the link is operating in Full-Duplex mode.
(8) Loopback Operation
The 10/100 digital has an independent loop-back mode: Internal loopback.
• Internal loopback
The internal loopback mode is enabled by setting bit register 0 bit 14 to logic one. In this
mode, the scrambled transmit data (output of the scrambler) is looped into the receive logic
(input of the descrambler). The CO_COL signal will be inactive in this mode, unless collision
test (bit 0.7) is active.
In this mode, during transmission (CO_TX_EN is HIGH), nothing is transmitted to the line
and the transmitters are powered down.
Rev. 6.00 Jul. 15, 2009 Page 664 of 816
REJ09B0237-0600