SH7619_09 Datasheet, PDF (561/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
0
BO
0
R/W Byte Order for Access of All HIF Registers Including
HIFDATA
Specifies the byte order when an external device
accesses all HIF registers including HIFDATA.
However, for the HIFDATA alignment, this bit is
referred to only when WBSWP = 0 and ignored when
WBSWP = 1. See also section 17.9, Alignment
Control.
0: Big endian (MSB first)
1: Little endian (LSB first)
17.4.4 HIF Memory Control Register (HIFMCR)
HIFMCR is a 32-bit register used to control HIFRAM. HIFMCR can be only read by the on-chip
CPU. Access to HIFMCR by an external device should be performed with HIFMCR specified by
bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Initial
Bit Bit Name Value
31 to 8 —
All 0
7
LOCK
0
6
—
0
R/W
R
R/W*
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Lock
This bit is used to lock the access direction (read or write)
for consecutive access of HIFRAM by an external device
via HIFDATA. When this bit is set to 1, the values of the
RD and WT bits set at the same time are held until this bit
is next cleared to 0. When the RD bit and this bit are
simultaneously set to 1, consecutive read mode is
entered. When the WT bit and this bit are simultaneously
set to 1, consecutive write mode is entered. Both the RD
and WT bits should not be set to 1 simultaneously.
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 6.00 Jul. 15, 2009 Page 521 of 816
REJ09B0237-0600