SH7619_09 Datasheet, PDF (53/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 1 Overview
Classifi-
cation Abbr.
I/O Pin Name Description
Serial
CTS1 and
Communi- CTS0
cation
interface
with FIFO
Input Transmit
Enable
Modem control pins. Supported only by SCIF0 and SCIF1.
Serial I/O SIOMCLK0 Input SIOF0 clock Master clock input pin
with FIFO
input
SCK_SIO0
Input/ SIOF0
output communication
clock
Input/output pin for communication clock common to
transmit/receive
SIOFSYNC0 Input/ SIOF0 frame Input/output pin for frame synchronization signal common to
output sync
transmit/receive
TXD_SIO0 Output SIOF0
Transmit data
transmit data
RXD_SIO0 Input SIOF0 receive Receive data
data
Host
HIFD15 to Input/ HIF Data Bus Address, data, and command input/output pins for the HIF.
interface HIFD00
output
HIFCS
Input HIF Chip
Select
Chip select input for the HIF.
HIFRS
Input HIF Register Controls the access type switching for the HIF.
Select
HIFWR
Input HIF Write
Write strobe signal
HIFRD
Input HIF Read
Read strobe signal
HIFINT
Output HIF Interrupt Interrupt request to external devices by the HIF.
HIFMD
Input HIF Mode
Specifies HIF boot mode.
HIFDREQ
Output HIF DMAC
Transfer
Request
Requests DMAC transfer for the HIFRAM to external devices.
HIFRDY
Output HIF Boot
Ready
Indicates that a reset of the HIF has been cleared in this LSI
and the HIF is ready for accesses to it.
HIFEBL
Input HIF Pin
Enable
HIF pins other than this pin are enabled by driving this pin
high.
Rev. 6.00 Jul. 15, 2009 Page 13 of 816
REJ09B0237-0600