SH7619_09 Datasheet, PDF (88/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 2 CPU
• Shift Instructions
Instruction
ROTL Rn
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAL Rn
SHAR Rn
SHLL Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
T ← Rn ← 0
MSB → Rn → T
T ← Rn ← 0
0 → Rn → T
Rn << 2 → Rn
Rn >> 2 → Rn
Rn << 8 → Rn
Rn >> 8 → Rn
Rn << 16 → Rn
Rn >> 16 → Rn
Code
Execution
Cycles
0100nnnn00000100 1
0100nnnn00000101 1
0100nnnn00100100 1
0100nnnn00100101 1
0100nnnn00100000 1
0100nnnn00100001 1
0100nnnn00000000 1
0100nnnn00000001 1
0100nnnn00001000 1
0100nnnn00001001 1
0100nnnn00011000 1
0100nnnn00011001 1
0100nnnn00101000 1
0100nnnn00101001 1
T Bit
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB





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• Branch Instructions
Instruction
BF label
BF/S label
BT label
BT/S label
Operation
If T = 0, disp × 2 + PC →
PC;
if T = 1, nop
Delayed branch, if T = 0,
disp × 2 + PC → PC;
if T = 1, nop
If T = 1, disp × 2 + PC →
PC;
if T = 0, nop
Delayed branch, if T = 1,
disp × 2 + PC → PC;
if T = 0, nop
Code
Execution
Cycles
10001011dddddddd 3/1*
T Bit

10001111dddddddd 2/1*

10001001dddddddd 3/1*

10001101dddddddd 2/1*

Rev. 6.00 Jul. 15, 2009 Page 48 of 816
REJ09B0237-0600