SH7619_09 Datasheet, PDF (688/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
22.5 100Base-TX Transmit
The data path of the 100Base-TX is shown in figure 22.6. Each major block is explained below.
CO_TX_CLK (for MII)
MAC
(Ether C)
MII 25 MHz
by 4 bits
MII
100 M
PLL
25 MHz
by 4 bits
4B/5B
encoder
25 MHz
by 5 bits
Scrambler
and PISO
125 Mbps Serial
NRZI
converter
NRZI
MLT-3
converter
MLT-3
Tx driver
MLT-3
Magnetics
RJ 45
MLT-3
MTL-3
CAT-5
Shaded blocks are
part of the PHY core
Figure 22.6 100Base-TX Data Path
(1) 100M Transmit Data across the MII
The MAC controller drives the transmit data onto the CO_MII_TXD bus and asserts the internal
signal (CO_TX_EN) to indicate valid data. The data is latched by the PHY's MII block on the
rising edge of CO_TX_CLK. The data is in the form of 4-bit wide 25MHz data.
(2) 4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data
from 4-bit nibbles to 5-bit symbols (known as "code-groups") according to table 22.2. Each 4-bit
data-nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are
either used for control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data
nibbles, 0 through F. The remaining code-groups are given letter designations with slashes on
either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
Rev. 6.00 Jul. 15, 2009 Page 648 of 816
REJ09B0237-0600