SH7619_09 Datasheet, PDF (714/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
2. Mechanism of Waveform Generation
Waveforms are generated in two ways; divided in time and voltage.
For an example of divisions in time and voltage, the case of a transfer from 0 V to 1 V in 4 ns
is shown below.
time
-----------
0
1 [ns]
2 [ns]
3 [ns]
Output voltage level
-----------------------------
250 [mv]
500 [mv]
750 [mv]
1 [v]
• Time ranges
In this case, four-divided time ranges are generated on internal clocks, at first. Rise times are
controlled as the divided numbers are controlled.
Total transition time is controlled as each timing in each time range is shifted on the DnSL bits
in the adjustment registers.
Each slope in each time range is set on the DnCMP bits.
• Voltage levels
The voltage levels are also divided in four. The levels are modified at once as the maximum
amplitude, the standard, is controlled on the DnA bits.
Rev. 6.00 Jul. 15, 2009 Page 674 of 816
REJ09B0237-0600