SH7619_09 Datasheet, PDF (541/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
(b) Cause of the Defect
After the transmission, the SIOF will be reset and initialized by setting the TXE bit in the
SICTR to ‘0’ with the SIOF master mode 1/2. However, if that SIOF fails to be reset, the
transmission will resume without the transmission module initialized and the defect mentioned
above will occur.
(c) Defect prevention
Please change the setting of SCK temporarily to make reset the modules using the CK clock
surely, specifically, whenever the TXE bit or the RXE bit in SICTR is set to ‘0’, please take
the procedures as follows;
(i) Set the Pφ as the master clock source.
(Set the MSSEL bit in SISCR to ‘1’ (master clock = Pφ).)
(ii) Set the master clock division ratio according with the count value of the prescalar of the
baud rate generator as ×1/1.
(Set the bits BRPS[4:0] in SISCR to ‘0000’ (as the master clock frequency ×1/1)).
(iii) Set the frequency division ratio for the output stage of the baud rate generator as ×1/1.
(Set the bits BRDV[2:0] in SISCR to ‘111’ (as the prescalar output frequency ×1/1).)
(iv) Reset the transmission/reception operation.
(Set the TXRST bit (or RXST bit) in the SICTR to ‘1’ (reset).)
(v) Set the value of SISCR for transmission/reception again, before start of next
transmission/reception.
Rev. 6.00 Jul. 15, 2009 Page 501 of 816
REJ09B0237-0600