SH7619_09 Datasheet, PDF (525/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16.4.6 FIFO
Overview: The transmit and receive FIFOs of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
Transfer Request: The transfer request of the FIFO can be issued to the CPU or DMAC as the
following interrupt sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the TFWM2 to TFWM0 bits and
RFWM2 to RFWM0 bits in SIFCTR, respectively. Tables 16.9 and 16.10 summarize the
conditions specified by SIFCTR.
Table 16.9 Conditions to Issue Transmit Request
TFWM2 to TFWM0
000
100
101
110
111
Number of
Requested Stages
1
4
8
12
16
Transmit Request
Used Areas
Empty area is 16 stages
Smallest
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more Largest
Table 16.10 Conditions to Issue Receive Request
RFWM2 to RFWM0
000
100
101
110
111
Number of
Requested Stages
1
4
8
12
16
Receive Request
Valid data is 1 stage or more
Valid data is 4 stages or more
Valid data is 8 stages or more
Valid data is 12 stages or more
Valid data is 16 stages
Used Areas
Smallest
Largest
Rev. 6.00 Jul. 15, 2009 Page 485 of 816
REJ09B0237-0600