SH7619_09 Datasheet, PDF (402/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
13.5.2 Notes On DREQ Sampling When DACK is Divided in External Access
(1) Error Phenomenon
When the DACK output is divided in an external access, DREQ may be sampled twice at
maximum in the external access.
(2) Error Conditions and Phenomenon
Conditions: The DACK output is divided in an external access when:
• 16-byte access,
• 32-bit access to the 8-bit space,
• 16-bit access to the 8-bit space, or
• 32-bit access to the 16-bit space
is performed with either of the following idle cycle settings made:
• Idle cycles between write-write cycles (IWW = 01 or more)
• Idle cycles between read-read cycles in the same spaces (IWRRS = 01 or more)
• External wait mask specification (WM = 0).
In addition to the above conditions, the following conditions are included depending on the
detection method of DREQ.
• For DREQ level detection: only write access
• For DREQ edge detection: both write access and read access
Phenomenon: The detection timings of the DREQ pin in the above access are shown in figures
13.19 to 13.22.
CKIO
Bus cycle
DREQ
(Rising edge)
DACK
(High-active)
CPU
1st acceptance
Non-sensitive period
DMAC write or read
2nd acceptance
Non-sensitive period
3rd acceptance possible
Figure 13.19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
When DACK is Divided to 4 by Idle Cycles
Rev. 6.00 Jul. 15, 2009 Page 362 of 816
REJ09B0237-0600