SH7619_09 Datasheet, PDF (25/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Figures
Section 1 Overview
Figure 1.1 Block Diagram .............................................................................................................. 7
Figure 1.2 Pin Assignments ............................................................................................................ 8
Section 2 CPU
Figure 2.1 CPU Internal Register Configuration .......................................................................... 24
Figure 2.2 Register Data Format................................................................................................... 28
Figure 2.3 Memory Data Format .................................................................................................. 28
Figure 2.4 CPU State Transition................................................................................................... 51
Section 3 Cache
Figure 3.1 Cache Structure ........................................................................................................... 53
Figure 3.2 Cache Search Scheme ................................................................................................. 58
Figure 3.3 Write-Back Buffer Configuration................................................................................ 59
Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access............................. 62
Section 6 Interrupt Controller (INTC)
Figure 6.1 INTC Block Diagram .................................................................................................. 84
Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control................................................... 98
Figure 6.3 Interrupt Sequence Flowchart.................................................................................... 103
Figure 6.4 Stack after Interrupt Exception Handling .................................................................. 104
Section 7 Bus State Controller (BSC)
Figure 7.1 Block Diagram of BSC.............................................................................................. 109
Figure 7.2 Address Space ........................................................................................................... 112
Figure 7.3 Normal Space Basic Access Timing (No-Wait Access)............................................ 149
Figure 7.4 Consecutive Access to Normal Space (1): Bus Width = 16 bits,
Longword Access, CSnWCR.WM = 0 (Access Wait = 0, Cycle Wait = 0) ............. 150
Figure 7.5 Consecutive Access to Normal Space (2): Bus Width = 16 bits,
Longword Access, CSnWCR.WM = 1 (Access Wait = 0, Cycle Wait = 0) ............. 151
Figure 7.6 Example of 32-Bit Data-Width SRAM Connection .................................................. 152
Figure 7.7 Example of 16-Bit Data-Width SRAM Connection .................................................. 153
Figure 7.8 Example of 8-Bit Data-Width SRAM Connection.................................................... 153
Figure 7.9 Wait Timing for Normal Space Access (Software Wait Only) ................................. 154
Figure 7.10 Wait Cycle Timing for Normal Space Access
(Wait cycle Insertion using WAIT)......................................................................... 155
Figure 7.11 Example of Timing when CSn Assertion Period is Extended ................................. 156
Figure 7.12 Example of 32-Bit Data-Width SDRAM Connection ............................................. 158
Figure 7.13 Example of 16-Bit Data-Width SDRAM Connection ............................................. 159
Rev. 6.00 Jul. 15, 2009 Page xxiii of xxxviii