SH7619_09 Datasheet, PDF (836/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Item
Page Revision (See Manual for Details)
Table 7.13 Relationship
161,
between Register Settings 162
(A3BSZ[1:0], A3ROW[1:0],
and A3COL[1:0]) and Address
Multiplex Output (2)
Deleted and amended
Setting
A2/3
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
Setting
A2/3
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
Table 7.14 Relationship
163 Deleted and amended
between Register Settings
(A3BSZ[1:0], A3ROW[1:0],
Setting
and A3COL[1:0]) and Address
A2/3
A3
A3
Multiplex Output (3)
BSZ
ROW
COL
[1:0]
[1:0]
[1:0]
Table 7.15 Relationship
164, Deleted
between Register Settings 165 _Setting
(A3BSZ[1:0], A3ROW[1:0],
and A3COL[1:0]) and Address
A3
A3
A3
Multiplex Output (4)
BSZ
[1:0]
ROW
[1:0]
COL
[1:0]
Setting
A3
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
Table 7.16 Relationship
165, Deleted
between Register Settings 166 _Setting
(A3BSZ[1:0], A3ROW[1:0],
and A3COL[1:0]) and Address
A3
A3
A3
Multiplex Output (5)
BSZ
[1:0]
ROW
[1:0]
COL
[1:0]
Setting
A3
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
Table 7.17 Relationship
167, Deleted
between Register Settings 168 _Setting
(A3BSZ[1:0], A3ROW[1:0],
and A3COL[1:0]) and Address
A3
A3
A3
Multiplex Output (6)
BSZ
[1:0]
ROW
[1:0]
COL
[1:0]
Setting
A3
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
11.4 Operation
253 Amended
The overview of the Ethernet controller (EtherC) are shown
below. The EtherC transmits and receives PAUSE frames
conforming to the Ethernet/IEEE802.3x frames.
Rev. 6.00 Jul. 15, 2009 Page 796 of 816
REJ09B0237-0600