SH7619_09 Datasheet, PDF (558/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
17.4.2 HIF General Status Register (HIFGSR)
HIFGSR is a 32-bit register, which can be freely used for handshaking between an external device
connected to the HIF and the software of this LSI. HIFGSR can be read from and written to by the
on-chip CPU. Reading from HIFGSR by an external device should be performed with the HIFRS
pin high, or HIFGSR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Writing
to HIFGSR by an external device should be performed with HIFGSR specified by bits REG5 to
REG0 in HIFIDX and the HIFRS pin low.
Bit
Bit Name
31 to 16 —
Initial
Value
All 0
15 to 0 STATUS15 to All 0
STATUS0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
General Status
This register can be read from and written to by an
external device connected to the HIF, and by the on-
chip CPU. These bits are initialized only at a power-
on reset.
17.4.3 HIF Status/Control Register (HIFSCR)
HIFSCR is a 32-bit register used to control the HIFRAM access mode and endian setting.
HIFSCR can be read from and written to by the on-chip CPU. Access to HIFSCR by an external
device should be performed with HIFSCR specified by bits REG5 to REG0 in HIFIDX and the
HIFRS pin low.
Bit
Bit Name
31 to 12 —
Initial
Value
All 0
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 6.00 Jul. 15, 2009 Page 518 of 816
REJ09B0237-0600