SH7619_09 Datasheet, PDF (44/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 1 Overview
Items
Specification
Clock pulse generator • Clock mode: Input clock can be selected from external input or crystal
(CPG)
resonator
• Three types of clocks generated:
 CPU clock: 125 MHz (max.)
 Bus clock: 62.5 MHz (max.)
 Peripheral clock: 31.25 MHz (max.)
• Supports power-down modes:
 Sleep mode
 Software standby mode
• Selection of four types of clock modes (PLL2 ×2/×4 and clock/crystal
resonator are selectable)
Ethernet controller
(EtherC)
• MAC (Media Access Control) function
 Data frame assembly/disassembly (frame format conforming to
IEEE802.3)
 CSMA/CD link management (collision prevention and collision
processing)
 CRC processing
 512 bytes each for transmit/receive FIFO
 Full-duplex transmit/receive support
 Short frame/long frame detectable
• Conforms to the MII (Media Independent Interface) standard
 Conversion from 8-bit stream data in MAC layer to MII nibble (4-bit)
stream
 Station management (STA function)
 18 TTL-level signals
 10/100 Mbps transfer rate adjustable
• Magic Packet^TM* (WOL (Wake-On-LAN) output)
Ethernet controller
DMAC (EDMAC)
• CPU load reduced with the descriptor management method
• For transferring from EtherC receive FIFO to receive buffer × 1 channel
• For transferring from transmit buffer to EtherC transmit FIFO × 1
channel
• 16-byte burst transfer improves the efficiency of system bus
• Supports single frame and multiple buffer
Rev. 6.00 Jul. 15, 2009 Page 4 of 816
REJ09B0237-0600