SH7619_09 Datasheet, PDF (379/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
13.3.6 DMA Extended Resource Selectors 0 and 1 (DMARS0 and DMARS1)
DMARS are 16-bit readable/writable registers that specify the DMA transfer request sources from
peripheral modules in each channel. DMARS0 specifies the sources for channels 0 and 1, and
DMARS1 specifies the sources for channels 2 and 3. This register can set the transfer request of
SCIF0, SCIF1, SCIF2, and SIOF0.
When MID/RID other than the values listed in table 13.2 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to
RS0) has been set to B'1000 for CHCR_0 to CHCR_3 registers. Otherwise, even if DMARS has
been set, transfer request source is not accepted.
• DMARS0
Initial
Bit
Bit Name Value R/W Description
15
C1MID5 0
14
C1MID4 0
13
C1MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 1
R/W ^(MID)
R/W ^{See table 13.2.}
12
C1MID2 0
R/W
11
C1MID1 0
R/W
10
C1MID0 0
R/W
9
C1RID1 0
8
C1RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 1
R/W ^(RID)
See table 13.2.
7
C0MID5 0
6
C0MID4 0
5
C0MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 0
R/W ^(MID)
R/W ^{See table 13.2.}
4
C0MID2 0
R/W
3
C0MID1 0
R/W
2
C0MID0 0
R/W
1
C0RID1 0
0
C0RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 0
R/W ^(RID)
See table 13.2.
Rev. 6.00 Jul. 15, 2009 Page 339 of 816
REJ09B0237-0600