|
SH7619_09 Datasheet, PDF (43/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series | |||
|
◁ |
Section 1 Overview
Items
Specification
Bus state controller
(BSC)
⢠Address space is divided into five areas: three areas 0, 3, and 4; each
a maximum of 64 Mbytes, and two areas 5B and 6B; each a maximum
of 32 Mbytes (address map 1 mode).
⢠Address space is divided into five areas, 0, 3, 4, 5, and 6; each a
maximum of 64 Mbytes (address map 2 mode).
⢠32-bit external bus (max.)
⢠The following features are settable for each area.
 Bus size (8, 16, or 32 bits) (Area 0 does not support the bus size of
32 bits.)
 Number of access wait cycles
 Setting of idle wait cycles
 Specifying the memory to be connected to each area enables direct
connection to SRAM, SDRAM, and PCMCIA.
 Outputs chip select signals (CS0, CS3, CS4, CS5B, and CS6B) for
corresponding area
⢠SDRAM refresh function
 Supports auto-refresh and self-refresh modes
⢠SDRAM burst access function
⢠PCMCIA access function
 Conforms to the JEIDA Ver. 4.2 standard, two slots
⢠Selection of big or little endian mode (The mode of all the areas is
switched collectively by a mode pin.)
Direct memory access ⢠Four channels; external request available for two of them
controller (DMAC)
⢠Burst mode and cycle steal mode
⢠Outputs a transfer end signal of the channel handling an external
request
⢠Intermittent mode available (16 and 64 cycles supported)
Interrupt controller
(INTC)
⢠Supports nine external interrupt pins (NMI, IRQ7 to IRQ0)
⢠On-chip peripheral interrupt: Priority level is independently selected for
each module
⢠Vector address: Specified vector address for each interrupt source
User debugging
interface (H-UDI)
⢠Supports the JTAG interface emulator
⢠JTAG standard pins arranged
Rev. 6.00 Jul. 15, 2009 Page 3 of 816
REJ09B0237-0600
|
▷ |