SH7619_09 Datasheet, PDF (45/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 1 Overview
Items
Specification
Ethernet physical layer • Conforms to the IEEE802.3u standard. 10Base-T and 100Base-TX
transceiver (PHY)
supported
• Supports Auto-negotiation and manual-negotiation modes
• Supports power-down modes
• Outputs the status of Link, Activity, Duplex, and Speed
• Selection of either on-chip clock oscillator output or dedicated clock
externally input
Host interface (HIF) • 1 kbyte × 2 banks: in total 2-kbyte buffer RAM
• The buffer RAM and the external device are connected in parallel via
16 data pins
• The buffer RAM and the CPU of this LSI are connected in parallel via
internal bus
• The external device can access the desired register after the register
index has been specified. (However, when the buffer RAM is accessed
successively, the address is updated automatically.)
• Selection of endian mode
• Interrupt requested to the external device
• Internal interrupt requested to the CPU of this LSI
• Booting from the buffer RAM is enabled if the external device has
stored the instruction code in the buffer RAM
Compare match timer • 16-bit counter
(CMT)
• Generates compare match interrupts
• Two channels
Serial communication • Synchronous and asynchronous modes
interface with FIFO
(SCIF)
• 16 bytes each for transmit/receive FIFO
• High-speed UART
• The UART supports FIFO stop and FIFO trigger
• Flow control enabled (channel 0 and channel 1 only)
• Three channels
Rev. 6.00 Jul. 15, 2009 Page 5 of 816
REJ09B0237-0600