SH7619_09 Datasheet, PDF (224/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
CKIO
CKE
Tp
Tpw
Trr
Trc
Trc
Trc
Trc
Trc
A25 to A0
A11*
CSn
RAS
CAS
RD/WR
DQMxx
D
Hi-z
BS
Note: * Address pin to be connected to pin A10 of SDRAM.
Figure 7.26 Self-Refreshing Timing
Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus
cycle execution, the refresh cycle must wait for the bus cycle to be completed.
If a new refresh request occurs while the previous refresh request is not performed, the previous
refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the
bus busy must be prevented.
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after turning the power on. To perform synchronous DRAM initialization correctly, the BSC
registers must first be set, followed by writing to the synchronous DRAM mode register. When
writing to the synchronous DRAM mode register, the address signal value at that time is latched
by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, write to
the address of H'F8FD5000 + X in words. In this operation, the data is ignored. To set burst
read/single write, burst read/burst write, CAS latency 2 to 3, wrap type = sequential, and burst
length 1 supported by the LSI, arbitrary data is written to the addresses shown in table 7.19 in
bytes. In this case, 0s are output at the external address pins of A12 or later.
Rev. 6.00 Jul. 15, 2009 Page 184 of 816
REJ09B0237-0600