SH7619_09 Datasheet, PDF (124/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 6 Interrupt Controller (INTC)
NMI
IRQ_... 0
IRQ7
UBC
H-UDI
WDT
E-DMAC
CMT0
CMT1
SCIF0
SCIF1
SCIF2
HIF
DMAC
SIOF
...
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
ICR0
IRQCR
IRQSR
Com-
parator
Priority
determination
IPR
IPRA to IPRE
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTER
DTC
Module bus
Bus
interface
[Legend]
UBC:
H-UDI:
WDT:
E-DMAC:
CMT:
SCIF:
INTC
User break controller
User debugging interface
Watchdog timer
DMAC for Ethernet controller
Compare match timer
Serial communications interface with FIFO
HIF:
Host interface
DMAC:
Direct memory access controller
ICR0:
Interrupt control register 0
IRQCR:
IRQ control register
IRQSR:
IRQ status register
IPRA to IPRG: Interrupt priority registers A to G
SR:
Status register
Figure 6.1 INTC Block Diagram
Rev. 6.00 Jul. 15, 2009 Page 84 of 816
REJ09B0237-0600