SH7619_09 Datasheet, PDF (16/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

11.4.1 Transmission..................................................................................................... 253
11.4.2 Reception .......................................................................................................... 255
11.4.3 MII Frame Timing ............................................................................................ 256
11.4.4 Accessing MII Registers................................................................................... 258
11.4.5 Magic Packet Detection .................................................................................... 261
11.4.6 Operation by IPG Setting.................................................................................. 262
11.4.7 Flow Control..................................................................................................... 262
11.5 Connection to PHY-LSI.................................................................................................... 263
11.6 Usage Notes ...................................................................................................................... 264
Section 12 Ethernet Controller Direct Memory Access Controller
(E-DMAC)....................................................................................... 267
12.1 Features............................................................................................................................. 267
12.2 Register Descriptions........................................................................................................ 268
12.2.1 E-DMAC Mode Register (EDMR) ................................................................... 269
12.2.2 E-DMAC Transmit Request Register (EDTRR) .............................................. 270
12.2.3 E-DMAC Receive Request Register (EDRRR)................................................ 271
12.2.4 Transmit Descriptor List Address Register (TDLAR)...................................... 272
12.2.5 Receive Descriptor List Address Register (RDLAR) ....................................... 272
12.2.6 EtherC/E-DMAC Status Register (EESR)........................................................ 273
12.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)................... 278
12.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)............................. 281
12.2.9 Receive Missed-Frame Counter Register (RMFCR) ........................................ 283
12.2.10 Transmit FIFO Threshold Register (TFTR)...................................................... 284
12.2.11 FIFO Depth Register (FDR) ............................................................................. 285
12.2.12 Receiving Method Control Register (RMCR) .................................................. 286
12.2.13 E-DMAC Operation Control Register (EDOCR) ............................................. 287
12.2.14 Receiving-Buffer Write Address Register (RBWAR) ...................................... 288
12.2.15 Receiving-Descriptor Fetch Address Register (RDFAR) ................................. 288
12.2.16 Transmission-Buffer Read Address Register (TBRAR)................................... 288
12.2.17 Transmission-Descriptor Fetch Address Register (TDFAR) ............................ 289
12.2.18 Flow Control FIFO Threshold Register (FCFTR) ............................................ 289
12.2.19 Transmit Interrupt Register (TRIMD) .............................................................. 290
12.3 Operation .......................................................................................................................... 291
12.3.1 Descriptor List and Data Buffers ...................................................................... 291
12.3.2 Transmission..................................................................................................... 300
12.3.3 Reception .......................................................................................................... 302
12.3.4 Multi-Buffer Frame Transmit/Receive Processing ........................................... 304
12.4 Usage Notes ...................................................................................................................... 306
12.4.1 Usage Notes on SH-Ether EtherC/E-DMAC Status Register (EESR).............. 306
Rev. 6.00 Jul. 15, 2009 Page xiv of xxxviii