SH7619_09 Datasheet, PDF (841/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Item
Page Revision (See Manual for Details)
Figure 22.1 The Block
632 Amended
Diagram around PHY Module
TX-CLK
MDC
MDIO
CO_TX_CLK
CO_MDC
CO_MDI
CO_MDO
22.4.1 Serial Management
Interface (SMI)
Figure 22.3 How to Derive
MDIO Signal from Core
Signals
635 Amended
The Serial Management Interface is used to control this
PHY core and obtain its status. This interface supports
registers 0 through 6 as required by Clause 22 of the
IEEE802.3 standard. Non-supported registers (7 to 15) will
be read as hexadecimal "FFFF".
635 Amended
ENB
CO_MDIO_DIR
CO_MDO
CO_MDI
22.4.1 Serial Management 635
Interface (SMI)
Figure 22.5 MDIO Timing and 636
Frame Structure (WRITE
Cycle)
Amended
The CO_MDC signal is an a-periodic clock provided by the
station management controller (SMC), part of the EtherC.
The CO_MDI signal receives serial data (commands) from
the controller SMC. The CO_MDO sends serial data
(status) to the SMC.
Amended
Output on the rising edge
Latch on the rising edge
...
R2 R1 R0
... ^{D15 D14}
D1 D0
ter Address
Turn
Around
Data
Rev. 6.00 Jul. 15, 2009 Page 801 of 816
REJ09B0237-0600