SH7046 Datasheet, PDF (82/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on
reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is
entered.
Exception Processing State: The exception processing state is a transient state that occurs when
exception processing sources such as resets or interrupts alter the CPU’s processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception processing vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception processing vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
Program Execution State: In the program execution state, the CPU sequentially executes the
program.
Power-Down State: In the power-down state, the CPU operation halts and power consumption
declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode.
Rev. 4.00 Dec 05, 2005 page 38 of 564
REJ09B0270-0400