SH7046 Datasheet, PDF (360/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 11 Watchdog Timer
11.6.5 System Reset by WDTOVF Signal
If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly.
Avoid logical input of the WDTOVF signal to the RES input pin. To reset the entire system with
the WDTOVF signal, use the circuit shown in figure 11.9.
Reset input
This LSI
RES
Reset signal to entire system
WDTOVF
Figure 11.9 Example of System Reset Circuit Using WDTOVF Signal
11.6.6 Internal Reset in Watchdog Timer Mode
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a
TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset.
11.6.7 Manual Reset in Watchdog Timer Mode
When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits
until the end of the bus cycle at the time of manual reset generation before making the transition to
manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a
manual reset occurs while the bus is released, manual reset exception processing will be deferred
until the CPU acquires the bus. However, if the interval from generation of the manual reset until
the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles,
the internal manual reset source is ignored instead of being deferred, and manual reset exception
processing is not executed.
11.6.8 Handling of WDTOVF Pin
Do not pull down the WDTOVF pin. If this pin needs to be pulled down, the pull-down resistance
value must be 1 MΩ or higher.
Rev. 4.00 Dec 05, 2005 page 316 of 564
REJ09B0270-0400