SH7046 Datasheet, PDF (582/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Appendix A Internal I/O Register
Register Name
Timer control/status register
Timer counter
Timer counter
Reset control/status register
Reset control/status register
Abbreviation Bits Address
TCSR
8
TCNT^*1
8
TCNT^*2
8
RSTCSR^*1 8
RSTCSR^*2 8
H'FFFF8610
H'FFFF8610
H'FFFF8611
H'FFFF8612
H'FFFF8613
Module
WDT
*1: Write
cycle
*2: Read
cycle
Access
Size
8^*2/16^*1
16
8
Access
States
In φ cycles
B: 3
W: 3
16
8
Standby control register
SBYCR
8 H'FFFF8614 Power- 8
down state
In φ cycles
B: 3


 H'FFFF8615 to


H'FFFF8617
System control register

SYSCR

Module standby control register 1 MSTCR1
8 H'FFFF8618
 H'FFFF8619 to
H'FFFF861B
16 H'FFFF861C
8

8, 16, 32
In Pφ cycles
B: 3
W: 3
L: 6
Module standby control register 2 MSTCR2
16 H'FFFF861E
8, 16
Bus control register 1

BCR1

16 H'FFFF8620 BSC
 H'FFFF8622 to
H’FFFF8626
8, 16, 32

In φ cycles
B: 3
W: 3
L: 6
RAM emulation register
RAMER
16 H’FFFF8628 FLASH
8, 16
In φ cycles
B: 3
W: 3

 H’FFFF862A to 


H’FFFF864F

 H’FFFF8650 to 


H’FFFF86FF
DTC enable register A
DTC enable register B
DTC enable register C
DTEA
DTEB
DTEC
8
H’FFFF8700 DTC
8 H’FFFF8701
8
H’FFFF8702
8, 16, 32
8
8, 16
In φ cycles
B: 3
W: 3
L: 6
DTC enable register D
DTED
8 H’FFFF8703
8

 H'FFFF8704 to

H'FFFF8705
DTC control/status register
DTCSR
16 H'FFFF8706
8, 16
DTC information base register DTBR
16 H'FFFF8708
8, 16

 H'FFFF870A to

H'FFFF870F
Rev. 4.00 Dec 05, 2005 page 538 of 564
REJ09B0270-0400