SH7046 Datasheet, PDF (467/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
Contention between Compare Register Write and Compare Match: If a compare match
occurs in the T2 state of a compare register (TGR or TPDR) write cycle, the compare register
write is not performed, and data is transferred from the buffer register (TBRU, TBRV, TBRW, or
TPBR) to the compare register by a buffer operation.
Figure 15.16 shows the timing in this case.
Pφ
Address
Write signal
Compare match
signal
Interrupt request
signal
Buffer register
Compare register
write cycle
T1 T2
Compare register
address
N
Compare register
N
Figure 15.16 Contention between Compare Register Write and Compare Match
Rev. 4.00 Dec 05, 2005 page 423 of 564
REJ09B0270-0400