SH7046 Datasheet, PDF (100/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 5 Exception Processing
Exception Sources
Vector Numbers Vector Table Address Offset
Trap instruction (user vector)
32
H'00000080–H'00000083
:
:
63
H'000000FC–H'000000FF
Interrupts IRQ0
64
H'00000100–H'00000103
IRQ1
65
H'00000104–H'00000107
IRQ2
66
H'00000108–H'0000010B
IRQ3
67
H'0000010C–H'0000010F
Reserved by system 68
H'00000110–H'00000113
Reserved by system 69
H'00000114–H'00000117
Reserved by system 70
H'00000118–H'0000011B
Reserved by system 71
On-chip peripheral module^*
72
H'0000011C–H'0000011F
H'00000120–H'00000123
:
:
255
H'000003FC–H'000003FF
Note: * The vector numbers and vector table address offsets for each on-chip peripheral
module interrupt are given in section 6, Interrupt Controller, and table 6.2, Interrupt
Exception Sources, Vector Addresses and Priorities.
Table 5.4 Calculating Exception Processing Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts,
instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
Rev. 4.00 Dec 05, 2005 page 56 of 564
REJ09B0270-0400