SH7046 Datasheet, PDF (107/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 5 Exception Processing
5.5.3 Illegal Slot Instructions
An instruction placed immediately after a delayed branch instruction is called “instruction placed
in a delay slot”. When the instruction placed in the delay slot is an undefined code, illegal slot
exception processing starts after the undefined code is decoded. Illegal slot exception processing
also starts when an instruction that rewrites the program counter (PC) is placed in a delay slot and
the instruction is decoded. The CPU handles an illegal slot instruction as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
3. The start address of the exception service routine is fetched from the exception processing
vector table that corresponds to the exception that occurred. That address is jumped to and the
program starts executing. The jump in this case is not a delayed branch.
5.5.4 General Illegal Instructions
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception processing starts. The CPU
handles the general illegal instructions in the same procedures as in the illegal slot instructions.
Unlike processing of illegal slot instructions, however, the program counter value that is stacked is
the start address of the undefined code.
Rev. 4.00 Dec 05, 2005 page 63 of 564
REJ09B0270-0400