SH7046 Datasheet, PDF (58/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
2.3.3 Immediate Data Format
Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV,
ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data.
Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
handled as longword data. Consequently, AND instructions with immediate data always clear the
upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code, but instead is stored in a
memory table. An immediate data transfer instruction (MOV) accesses the memory table using the
PC relative addressing mode with displacement.
2.4 Instruction Features
2.4.1 RISC-Type Instruction Set
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per State: The microprocessor can execute basic instructions in one state using
the pipeline system. One state is 25 ns at 40 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data.
Table 2.2 Sign Extension of Word Data
CPU of This LSI
Description
Example of Conventional CPU
MOV.W
ADD
.DATA.W
@(disp,PC),R1
R1,R0
.........
H'1234
Data is sign-extended to 32 ADD.W
bits, and R1 becomes
H'00001234. It is next operated
upon by an ADD instruction.
#H'1234,R0
Note: @(disp, PC) accesses the immediate data.
Rev. 4.00 Dec 05, 2005 page 14 of 564
REJ09B0270-0400