SH7046 Datasheet, PDF (37/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Figure 14.8 CMCNT Byte Write and Increment Contention .................................................. 395
Section 15 Motor Management Timer (MMT)
Figure 15.1 Block Diagram of MMT ...................................................................................... 398
Figure 15.2 Sample Operating Mode Setting Procedure......................................................... 407
Figure 15.3 Example of TCNT Count Operation .................................................................... 408
Figure 15.4 Examples of Counter and Register Operations .................................................... 410
Figure 15.5 Example of PWM Waveform Generation............................................................ 413
Figure 15.6 Example of TCNT Counter Clearing ................................................................... 414
Figure 15.7 Example of Toggle Output Waveform Synchronized with PWM Cycle ............. 415
Figure 15.8 Count Timing....................................................................................................... 417
Figure 15.9 TCNT Counter Clearing Timing.......................................................................... 417
Figure 15.10 TDCNT Operation Timing .................................................................................. 418
Figure 15.11 Buffer Operation Timing ..................................................................................... 419
Figure 15.12 TGI Interrupt Timing ........................................................................................... 420
Figure 15.13 Timing of Status Flag Clearing by CPU .............................................................. 421
Figure 15.14 Timing of Status Flag Clearing by DTC Controller............................................. 421
Figure 15.15 Contention between Buffer Register Write and Compare Match ........................ 422
Figure 15.16 Contention between Compare Register Write and Compare Match .................... 423
Figure 15.17 Writing into Timer General Registers (When One Cycle is Not Output) ............ 424
Figure 15.18 Block Diagram of POE ........................................................................................ 426
Figure 15.19 Low Level Detection Operation........................................................................... 430
Section 17 I/O Ports
Figure 17.1 Port A................................................................................................................... 449
Figure 17.2 Port B ................................................................................................................... 451
Figure 17.3 Port E ................................................................................................................... 453
Figure 17.4 Port F ................................................................................................................... 456
Figure 17.5 Port G................................................................................................................... 457
Section 18 Flash Memory (F-ZTAT Version)
Figure 18.1 Block Diagram of Flash Memory ....................................................................... 460
Figure 18.2 Flash Memory State Transitions .......................................................................... 461
Figure 18.3 Boot Mode ........................................................................................................... 462
Figure 18.4 User Program Mode............................................................................................. 463
Figure 18.5 Flash Memory Block Configuration .................................................................... 464
Figure 18.6 Programming/Erasing Flowchart Example in User Program Mode..................... 473
Figure 18.7 Flowchart for Flash Memory Emulation in RAM................................................ 474
Figure 18.8 Example of RAM Overlap Operation (RAM[2:0] = b'000) ................................. 475
Figure 18.9 Program/Program-Verify Flowchart .................................................................... 477
Figure 18.10 Erase/Erase-Verify Flowchart.............................................................................. 479
Rev. 4.00 Dec 05, 2005 page xxxvii of xliv