SH7046 Datasheet, PDF (168/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
8.3.6 DTC Execution State Counts
Table 8.5 shows the execution state for one DTC data transfer. Furthermore, Table 8.6 shows the
state counts needed for execution state.
Table 8.5 Execution State of DTC
Mode
Vector Read
I
Register
Information
Read/Write
J
Data Read
K
Normal
1
7
1
Repeat
1
7
1
Block transfer 1
7
N
Note: N means a block size (default set values of DTCRB)
Data Write
L
1
1
N
Internal
Operation
M
1
1
1
Table 8.6 State Counts Needed for Execution State
Access Objective
On-chip On-chip
RAM
ROM
Bus width
32
32
Access state
1
1
Execution Vector read
S
I

1
state
Register information read/write S_J
1
1
Byte data read
S_K
1
1
Word data read
S_K
1
1
Longword data read
S
1
1
K
Byte data write
S
1
1
L
Word data write
S_L
1
1
Longword data write
S_L
1
1
Internal operation
S_M
1
1
Notes: 1. Two state access modules: Port, INT, CMT, SCI, etc.
2. Three state access modules: WDT, UBC, etc.
Internal I/O Register
32
32
2^*1
3^*2




2
3
2
3
4
6
2
3
2
3
4
6
1
1
The execution state count is calculated using the following formula. Σ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is set to 1).
Execution state count = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
Rev. 4.00 Dec 05, 2005 page 124 of 564
REJ09B0270-0400