SH7046 Datasheet, PDF (131/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
Interrupt acceptance
1
3
5 + m1 + m2 + m3
3
m1 m2 1 m3 1
IRQ
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
Interrupt service routine
start instruction
F DE E MMEME E
F
FDE
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed according to the results
of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted
6.8 Data Transfer with Interrupt Request Signals
The following data transfers can be done using interrupt request signals:
• Activate DTC only, CPU interrupts according to DTC settings
The INTC masks CPU interrupts when the corresponding DTE bit is 1. The conditions for clearing
DTE and interrupt source flag are listed below.
DTE clear condition = DTC transfer end • DTECLR
Interrupt source flag clear condition = DTC transfer end • DTECLR
Where: DTECLR = DISEL + counter 0.
Figure 6.6 shows a control block diagram.
Rev. 4.00 Dec 05, 2005 page 87 of 564
REJ09B0270-0400