SH7046 Datasheet, PDF (104/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 5 Exception Processing
5.3.2 Address Error Exception Processing
When an address error occurs, the bus cycle in which the address error occurred ends, the current
instruction finishes, and then address error exception processing starts. The CPU operates as
follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
3. The start address of the exception service routine is fetched from the exception processing
vector table that corresponds to the occurred address error, and the program starts executing
from that address. The jump in this case is not a delayed branch.
5.4 Interrupts
5.4.1 Interrupt Sources
Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, user
breaks, IRQ and on-chip peripheral modules.
Table 5.7 Interrupt Sources
Type
NMI
User break
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller
IRQ0–IRQ3 pins (external input)
Multifunction timer unit
Data transfer controller
Compare match timer
A/D converter (A/D0 and A/D1)
A/D converter (A/D2)
Serial communication interface
Watchdog timer
Motor management timer
Input/output Port
Number of Sources
1
1
4
23
1
2
2
1
8
1
2
2
Rev. 4.00 Dec 05, 2005 page 60 of 564
REJ09B0270-0400